For manufacturers of consumer electronics, conformance testing of embedded software is a vital issue. To improve performance, parts of this software are implemented in hardware, often designed in the Hardware Description Language VHDL. Conformance testing is a time consuming and error-prone process. Thus automating (parts of) this process is essential. There are many tools for test generation and for VHDL simulation. However, most test generation tools operate on a high level of abstraction and applying the generated tests to a VHDL design is a complicated task. For each specific case one can build a layer of dedicated circuitry and/or software that performs this task. It appears that the ad-hoc nature of this layer forms the bottleneck of the testing process. We propose a {em generic solution for bridging this gap: a generic layer of software dedicated to interface with VHDL implementations. It consists of a number of Von Neumann-like components that can be instantiated for each specific VHDL design. This paper reports on the construction of and some initial experiences with a concrete tool environment based on these principles.

Reliability and Testing (acm B.6.2), Reliability and Testing (acm B.7.3), Network Protocols (acm C.2.2), Testing and Debugging (acm D.2.5), Models of Computation (acm F.1.1)
Reliability, testing and fault tolerance (msc 68M15), Theory of computing (msc 68Qxx), None of the above, but in MSC2010 section 91Cxx (msc 91C99), Fault detection; testing (msc 94C12), Applications of graph theory (msc 94C15)
Software Engineering [SEN]

Moonen, J.R, Romijn, J.M.T, Sies, O, Springintveld, J.G, Feijs, L.M.G, & Koymans, R.L.C. (1997). A two-level approach to automated conformance testing of VHDL designs. Software Engineering [SEN]. CWI.