Hardware-Oblivious Parallelism for In-Memory Column-Stores
Presented at the International Conference on Very Large Databases, Riva del Garda, Italy
The multi-core architectures of today’s computer systems make parallelism a necessity for performance critical applications. Writing such applications in a generic, hardware-oblivious manner is a challenging problem: Current database systems thus rely on labor-intensive and error-prone manual tuning to exploit the full potential of modern parallel hardware architectures like multi-core CPUs and graphics cards. We propose an alternative design for a parallel database engine, based on a single set of hardware-oblivious operators, which are compiled down to the actual hardware at runtime. This design reduces the development overhead for parallel database engines, while achieving competitive performance to hand-tuned systems. We provide a proof-of-concept for this design by integrating operators written using the parallel programming framework OpenCL into the open-source database MonetDB. Following this approach, we achieve efficient, yet highly portable parallel code without the need for optimization by hand. We evaluated our implementation against MonetDB using TPC-H derived queries and observed a performance that rivals that of MonetDB’s query execution on the CPU and surpasses it on the GPU. In addition, we show that the same set of operators runs nearly unchanged on a GPU, demonstrating the feasibility of our approach.
|Information (theme 2)|
|Proceedings of the VLDB Endowment|
|International Conference on Very Large Databases|
Heimel, M, Saecker, M, Pirk, H, Manegold, S, & Markl, V. (2013). Hardware-Oblivious Parallelism for In-Memory Column-Stores. In Proceedings of the VLDB Endowment.